This invention relates generally to semiconductor manufacture, and more particularly to an improved test carrier and interconnect for temporarily packaging and testing semiconductor components, such as dice and chip scale packages. This invention also relates to a method for fabricating the carrier and the interconnect.
Semiconductor components, such as bare dice and chip scale packages, must be tested prior to shipment by semiconductor manufacturers. Since these components are relatively small and fragile, carriers have been developed for temporarily packaging the components for testing. The carriers permit electrical connections to be made between external contacts on the components, and testing equipment such as burn-in boards.
An interconnect on the carrier includes contacts that make the temporary electrical connections with the external contacts on the components. On bare dice, the external contacts typically comprise planar or bumped bond pads. On chip scale packages, the external contacts typically comprise solder balls in a dense array, such as a ball grid array, or a fine ball grid array.
One problem that can occur with a temporary carrier is flexure of the component in the assembled carrier. Typically, a force applying mechanism of the carrier, such as a spring, presses the component against the interconnect. In order to insure physical and electrical contact between the external contacts on the component and the interconnect contacts, the force applying mechanism must exert a relatively large biasing force on the component. This large biasing force can sometimes cause the component to flex or bow. This flexure can cause some of the external contacts on the component to pull away from the interconnect contacts. Worse yet, the flexure can cause cracking and damage to the component.
FIGS. 1A-1C illustrates a prior art test carrier 10 constructed to temporarily package a semiconductor component 14 for testing. In this case the component 14 comprises a bare semiconductor die. The test carrier 10 is further described in U.S. Pat. No. 5,519,332 to Wood et al., entitled xe2x80x9cCarrier For Testing An Unpackaged Semiconductor Diexe2x80x9d, which is incorporated herein by reference.
The test carrier 10 includes a base 12 and an interconnect 16 mounted to the base 12. In addition, the test carrier 10 includes a bridge clamp 18, a spring 20 and a pressure plate 22, adapted to bias the component 14 against the interconnect 16.
As shown in FIGS. 1B and 1C, the interconnect 16 includes interconnect contacts 26 adapted to electrically engage component contacts 28 (FIG. 1C) on the component 14. For example, the component contacts 28 can comprise thin film aluminum bond pads in electrical communication with integrated circuits on the component 14. The interconnect contacts 26 are in electrical communication with conductors 30 and bond pads 32 on the interconnect 16.
The interconnect 16 also includes an insulating layer 36 (FIG. 1C) for electrically insulating the interconnect contacts 26 and conductors 30. In addition, wires 24 (FIG. 1A) are bonded to the bond pads 32 on the interconnect 16, and electrically connect the interconnect contacts 26 to terminal contacts 34 (FIG. 1A) on the base 12 of the carrier 10.
The interconnect 16 is further described in U.S. Pat. No. 5,686,317 to Akram et al. entitled xe2x80x9cMethod For Forming An Interconnect Having A Penetration Limited Contact Structure For Establishing A Temporary Electrical Connection With A Semiconductor Diexe2x80x9d, which is incorporated herein by reference.
As shown in FIG. 1D, the component 14 can sometimes flex, or bow, under pressure from the spring 20 (FIG. 1A) and pressure plate 22 (FIG. 1A). This flexure can cause the component contacts 28 to pull away from the interconnect contacts 26. In addition, this flexure can cause damage to the component 14.
The present invention is directed to an improved test carrier and interconnect that are constructed to prevent flexure and bowing of a component under test.
In accordance with the present invention, an improved test carrier and interconnect are provided. The test carrier can be used to temporarily package and test a semiconductor component, without flexure of the component in the assembled carrier. The component can comprise a bare die, or a chip scale package.
The carrier includes a base for mounting the interconnect, and a force applying mechanism for biasing the component against the interconnect. The interconnect includes a substrate, and contacts formed on the substrate configured to electrically engage contacts on the component. For planar component contacts (e.g., bond pads on a bare die), the interconnect contacts can comprise raised members having penetrating projections covered with conductive layers. For bumped component contacts (e.g., solder balls on a chip scale package), the interconnect contacts can comprise indentations covered with conductive layers.
The interconnect also includes support members configured to physically contact a surface of the component, to prevent flexure of the component while biasing pressure is exerted by the force applying mechanism. In an illustrative embodiment, the support members comprise raised pillars having a planar surface for engaging the surface of the component. In addition, the support members can include an elastomeric layer to provide cushioning, and to accommodate Z-direction dimensional variations in the component contacts. Further, the support members can be arranged to engage the component along edges thereof, in areas formed by streets, or scribe lines, of the component. In addition, the components can be provided with contact pads for physically engaging the support members on the interconnect. In an alternate embodiment, the support members are configured to physically contact a pressure plate of the force applying mechanism rather than the component.
In a first carrier embodiment the carrier base includes terminal contacts, and the interconnect is wire bonded to the base, with the interconnect contacts in electrical communication with the terminal contacts on the base. In a second carrier embodiment, the interconnect includes conductive vias and external ball contacts in electrical communication with the interconnect contacts. In the second carrier embodiment, the interconnect can be molded to the base with the external ball contacts exposed, to provide the terminal contacts for the carrier. In a third carrier embodiment the support members are formed on the carrier base rather than on the interconnect.
A method for fabricating the interconnect includes the steps of providing a substrate, and etching the substrate to form the interconnect contacts and support members. Conductive layers can then be deposited on the interconnect contacts, and if desired, an elastomeric layer can be deposited on the support members. For fabricating the interconnect with conductive vias, a laser machining process can be used to form openings in the substrate. The laser machined openings can then be filled with a conductive material, and ball contacts attached to the filled openings by soldering, brazing or welding pre-formed metal balls. Alternately a deposition process such as electroless or electrolytic plating can be used to form the ball contacts.